The present invention relates in general to integrated circuits (ICs), and in particular to a charge pump circuit that from a primary voltage source generates a secondary voltage that is larger in absolute magnitude.
Many electronic systems require more than a single power supply voltage level for operation. For example, certain types of non-volatile memory circuits that may typically use a single 5 volt supply as the primary source of power, often also require higher voltages of, e.g., 10 to 15 volts for programming or erasing functions. Similarly, circuits developed for use in communication and networking systems often require voltages other than the primary supply voltage to, for example, meet certain interface specifications.
Depending on the power requirements of such secondary supply voltages, it is desirable to generate them internally from the primary power supply. This eliminates the need for additional externally provided power supplies. To this end, voltage multiplying or charge pump circuits have been developed that generate the higher voltages from the primary supply voltage.
Charge pump circuits take advantage of the charge storing capability of capacitors to, for example, double the level of a primary supply voltage by bootstrapping. A typical example of a charge pump circuit for use in communication circuits is disclosed in U.S. Pat. No. 4,797,899. There, a network of switches and capacitors operate to generate voltages twice that of the primary Vdd supply in both positive (+2 Vdd) and negative (-2 Vdd) directions.
In certain applications, it may be necessary to generate a voltage that is more negative than the substrate voltage Vss, and the substrate cannot be pumped to a more negative voltage than Vss. Driving a transmission line termination switch, for example, may give rise to such a condition. Consider a computing system such as a personal computer (PC) or a computer workstation within which an IC may receive input signals with amplitude of, for example, .+-.10 volts. FIG. 1 illustrates a transmission line 100 carrying a .+-.10 volt signal to an IC that may be powered by .+-.5 volt supplies. Transmission line 100 is terminated by a conventional termination circuit 102. Termination circuit 102 includes a pair of 50.OMEGA. resistors separated by a termination switch 104.
It is desirable to integrate termination switch 104 inside the receiver IC. FIG. 2A shows one example of how termination switch 104 can be implemented by a complementary metal-oxide-semiconductor (CMOS) switch including an N-channel transistor (NMOS) 200 and a P-channel transistor (PMOS) 202. The CMOS switch, however, will not operate properly if the IC is powered by .+-.5 volt supplies and the input signal range is .+-.10 volts. Given a p-type substrate that is biased at -5 volts, a negative voltage of -7 or -10 volts applied to the source/drain terminals of NMOS 200 would turn on the source/drain junction diodes of the transistor as shown in FIG. 2B. This may cause severe over-current conditions due to latch-up. To avoid this condition, the substrate voltage must be reduced to as low as the lowest voltage in the chip which may be as low as -12 volts. Given a +5 volt positive supply, this would place 17 volts across transistor source/drain junctions. For a typical CMOS process 17 volts approaches junction breakdown voltage levels. Reducing substrate voltage down to such levels therefore is not an option.
Because PMOS 202 is inside a separate n-well (not shown) that can be independently biased, given the above voltage conditions, switch 104 can be implemented using only a single PMOS transistor. However, the circuit driving the gate terminal of PMOS 202 would need to operate from a different power supply. This is because the .+-.5 volt internal supply levels will not be able to turn PMOS 202 on and off with .+-.10 volts at its source/drain terminals. Voltage levels of, for example, .+-.12 volts would be required to drive the gate of PMOS 202. An internal charge pump circuit is typically used to generate the necessary voltages from the power supplies.
Conventional charge pump circuits such as those described in the above-referenced U.S. Pat. No. 4,797,899, use NMOS transistors to generate the output voltage. Similar constraints as described above with respect to breakdown voltages, threshold voltages and latch-up conditions would therefore apply to the NMOS transistor in the charge pump circuit. Thus, it is not possible to use conventional charge pump circuitry that include NMOS transistors in applications such as described above.
There is therefore a need for a charge pump circuit that is capable of generating a voltage more negative than the substrate voltage Vss in a circuit where the substrate cannot be pumped to more negative than Vss. A similar need exists for a charge pump circuit that operates with the opposite polarity.